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lt3800 1 3800fb typical applicatio u applicatio s u features wide 4v to 60v input voltage range output voltages up to 36v adaptive nonoverlap circuitry prevents switch shoot-through reverse inductor current inhibit for discontinuous operation improves efficiency with light loads output slew rate controlled soft-start with auto-reset 100 a no load quiescent current low 10 a current shutdown 1% regulation accuracy 200khz operating frequency standard gate n-channel power mosfets current limit unaffected by duty cycle reverse overcurrent protection 16-lead thermally enhanced tssop package high-voltage synchronous current mode step-down controller the lt 3800 is a 200khz fixed frequency high voltage synchronous current mode step-down switching regula- tor controller. the ic drives standard gate n-channel power mosfets and can operate with input voltages from 4v to 60v. an onboard regulator provides ic power directly from v in and provides for output-derived power to minimize v in quiescent current. mosfet drivers employ an internal dynamic bootstrap feature, maximizing gate-source ?n voltages during normal operation for improved operating efficiencies. the lt3800 incorporates burst mode opera- tion, which reduces no load quiescent current to under 100 a. light load efficiencies are also improved through a reverse inductor current inhibit, allowing the controller to support discontinuous operation. both burst mode operation and the reverse-current inhibit features can be disabled if desired. the lt3800 incorporates a program- mable soft-start that directly controls the voltage slew rate of the converter output for reduced startup surge currents and overshoot errors. the lt3800 is available in a 16-lead thermally enhanced tssop package. descriptio u 12v and 42v automotive and heavy equipment 48v telecom power supplies avionics and industrial control systems distributed power converters 12v 75w dc/dc converter with reverse current inhibit and input uvlo efficiency and power loss , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6611131, 6304066, 6498466, 6580258. v in shdn c ss burst_en v fb v c sense boost tg sw v cc bg pgnd sense + lt3800 sgnd 1.5nf 200k 100pf 680pf 174k 1% 20k 1% 82.5k 1m 82.5k 0.015 ? bas19 1n4148 1 f 1 f 1 f 3 56 f 2 + 10 f 270 f + si7850dp si7370dp b160 15 h v in 20v to 55v v out 12v at 75w 3800 ta01a i load (a) efficiency (%) power loss (w) 100 95 90 3800 ta01b 70 75 85 80 6 5 4 0 1 3 2 10 0.1 1 v in = 24v loss (48v) v in = 48v v in = 60v v in = 36v
lt3800 2 3800fb fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 v in nc shdn c ss burst_en v fb v c sense boost tg sw nc v cc bg pgnd sense + 17 supply voltages input supply pin (v in ) .............................. 0.3v to 65v boosted supply pin (boost) ................... 0.3v to 80v boosted supply voltage ( boost sw) .. 0.3v to 24v boosted supply reference pin (sw) ........... 2v to 65v local supply pin (v cc ) ............................. 0.3v to 24v input voltages sense + , sense ...................................... 0.3v to 40v sense + ?sense ......................................... 1v to 1v burst_en pin ......................................... 0.3v to 24v other inputs (shdn, c ss , v fb , v c ) .......... 0.3v to 5.0v input currents shdn, c ss ............................................... 1ma to 1ma maximum temperatures operating junction temperature range (note 2) lt3800e (note 3) ............................. 40 c to 125 c lt3800i ............................................ 40 c to 125 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c t jmax = 125 c, ja = 40 c/w, jc = 10 c/w exposed pad (pin 17) is sgnd must be soldered to pcb absolute axi u rati gs w ww u electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, sense = sense + = 10v, sgnd = pgnd = sw = 0v, ctg = cbg = 3300pf, unless otherwise noted. symbol parameter conditions min typ max units v in operating voltage range (note 4) 460v minimum start voltage 7.5 v uvlo threshold (falling) 3.65 3.80 3.95 v uvlo hysteresis 670 mv i vin v in supply current v cc > 9v 20 a v in burst mode current v burst_en = 0v, v fb = 1.35v 20 a v in shutdown current v shdn = 0v 815 a v boost operating voltage 75 v operating voltage range (note 5) v boost ?v sw 20 v uvlo threshold (rising) v boost ?v sw 5v uvlo hysteresis v boost ?v sw 0.4 v pi co figuratio uuu order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ lead free finish tape and reel part marking package description temperature range lt3800efe#pbf lt3800efe#trpbf 3800efe 16-lead plastic tssop 40 c to 125 c lt3800ife#pbf lt3800ife#trpbf 3800ife 16-lead plastic tssop 40 c to 125 c (note 1)
lt3800 3 3800fb symbol parameter conditions min typ max units i boost boost supply current (note 6) 1.4 ma boost burst mode current v burst_en = 0v 0.1 a boost shutdown current v shdn = 0v 0.1 a v cc operating voltage (note 5) 20 v output voltage 8.0 8.3 v uvlo threshold (rising) 6.25 v uvlo hysteresis 500 mv i vcc v cc supply current (note 6) 3 3.6 ma v cc burst mode current v burst_en = 0v 80 a v cc shutdown current v shdn = 0v 20 a short-circuit current 40 120 ma v shdn enable threshold (rising) 1.30 1.35 1.40 v threshold hysteresis 120 mv v sense common mode range 036 current limit sense voltage v sense + ?v sense 140 150 175 mv reverse protect sense voltage v sense + ?v sense , v burst_en = v cc 150 mv reverse current offset v burst_en = 0v or v burst_en = v fb 10 mv i sense input current v sense(cm) = 0v 0.8 ma (i sense + + i sense )v sense(cm) = 2.75v 20 a v sense(cm) > 4v 0.3 ma f o operating frequency 190 200 210 khz 175 220 khz v fb error amp reference voltage measured at v fb pin 1.224 1.231 1.238 v 1.215 1.245 v i fb feedback input current 25 na v fb(ss) soft-start disable voltage v fb rising 1.185 v soft-start disable hysteresis 300 mv i css soft-start capacitor control current 2 a g m error amp transconductance 275 350 400 mhos a v error amp dc voltage gain 62 db v c error amp output range zero current to current limit 1.2 v i vc error amp sink/source current 30 a v tg,bg gate drive output on voltage (note 7) 9.8 v gate drive output off voltage 0.1 v t tg,bg gate drive rise/fall time 10% to 90% or 90% to 10% 50 ns t tg(off) minimum off time 450 ns t tg(on) minimum on time 300 500 ns t nol gate drive nonoverlap time tg fall to bg rise 200 ns bg fall to tg rise 150 ns electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, sense = sense + = 10v, sgnd = pgnd = sw = 0v, ctg = cbg = 3300pf, unless otherwise noted.
lt3800 4 3800fb typical perfor a ce characteristics uw i cc current limit vs temperature shutdown threshold (rising) vs temperature v cc vs temperature shutdown threshold (falling) vs temperature v cc vs i cc(load) v cc vs v in temperature ( c) ?0 ?5 1.37 1.36 1.35 1.34 1.33 100 3800 g01 0 50 125 25 75 shutdown threshold, rising (v) ?0 ?5 100 0 50 125 25 75 temperature ( c) 1.240 1.235 1.230 1.225 1.220 3800 g02 shutdown threshold, falling (v) temperature ( c) ?0 ?5 v cc (v) 8.0 8.1 7.8 7.9 125 3800 g03 0 50 25 75 100 i cc = 0ma i cc = 20ma i cc(load) (ma) 0 v cc (v) 40 3800 g04 10 20 30 8.05 8.00 7.95 7.90 7.85 51525 35 t a = 25 c v in (v) 4 v cc (v) 8 7 6 5 4 3 79 12 3800 g05 56 8 10 11 i cc = 20ma t a = 25 c ?0 ?5 100 0 50 125 25 75 temperature ( c) 200 175 150 125 100 75 50 3800 g06 i cc current limit (ma) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 3: the lt3800e is guaranteed to meet performance specifications from 0 c to 125 c junction temperature. specifications over the 40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3800i is guaranteed over the full 40 c to 125 c operating junction temperature range. note 4: v in voltages below the start-up threshold (7.5v) are only supported when v cc is externally driven above 6.5v. note 5: operating range dictated by mosfet absolute maximum gate- source voltage ratings. note 6: supply current specification does not include switch drive currents. actual supply currents will be higher. note 7: dc measurement of gate drive output ?n?voltage is typically 8.6v. internal dynamic bootstrap operation yields typical gate ?n voltages of 9.8v during standard switching operation. standard operation gate ?n?voltage is not tested but guaranteed by design. electrical characteristics
lt3800 5 3800fb operating frequency vs temperature typical perfor a ce characteristics uw uu u pi fu ctio s v in (pin 1): converter input supply. nc (pin 2): no connection. shdn (pin 3): precision shutdown pin. enable threshold is 1.35v (rising) with 120mv of input hysteresis. when in shutdown mode, all internal ic functions are disabled. the precision threshold allows use of the shdn pin to incor- porate uvlo functions. if the shdn pin is pulled below 0.7v, the ic enters a low current shutdown mode with i vin < 10 a. in low-current shutdown, the ic will sink 20 a from the v cc pin until that local supply has collapsed. typical pin input bias current is <10na and the pin is internally clamped to 6v. c ss (pin 4): soft-start ac coupling capacitor input. connect capacitor (c ss ) in series with a 200k resistor from pin to converter output (v out ). controls converter start- up output voltage slew rate ( ? v out / ? t). slew rate corre- sponds to 2 a average current through the soft-start coupling capacitor. the capacitor value for a desired output startup slew rate follows the relation: c ss = 2 a/( ? v out / ? t) shorting this pin to sgnd disables the soft-start function burst_en (pin 5): burst mode operation enable pin. this pin also controls reverse-inhibit mode of operation. when the pin voltage is below 0.5v, burst mode operation error amp reference vs temperature i (sense + + sense ) vs v sense(cm) v sense(cm) (v) 0 0.5 1.5 2.5 3.5 4.5 i (sense + + sense ) ( a) 800 600 400 200 0 ?00 ?00 1.0 2.0 3.0 4.0 3800 g09 5.0 t a = 25 c temperature ( c) 3800 g10 ?0 220 210 200 190 180 ?5 operating frequency (khz) 100 0 50 125 25 75 ?0 ?5 100 0 50 125 25 75 temperature ( c) error amp reference (v) 1.232 1.231 1.230 1.229 1.228 1.227 3800 g11 v cc uvlo threshold (rising) vs temperature error amp transconductance vs temperature temperature ( c) ?0 ?5 100 3800 g07 0 50 125 25 75 6.30 6.25 6.20 6.15 v cc uvlo threshold, rising (v) i cc vs v cc (shdn = 0v) v cc (v) 0 i cc ( a) 15 20 25 16 3800 g12 10 5 0 246 810 12 14 18 20 t a = 25 c temperature ( c) ?0 ?5 100 0 50 125 25 75 380 360 340 320 3800 g08 error amp transconductance ( mho)
lt3800 6 3800fb and reverse-current inhibit functions are enabled. when the pin voltage is above 0.5v, burst mode operation is disabled, but reverse-current inhibit operation is main- tained. dc/dc converters operating with reverse-current inhibit operation (burst_en = v fb ) have a 1ma minimum load requirement. reverse-current inhibit is disabled when the pin voltage is above 2.5v. this pin is typically shorted to ground to enable burst mode operation and reverse- current inhibit, shorted to v fb to disable burst mode operation while enabling reverse-current inhibit, and con- nected to v cc pin to disable both functions. see applica- tions information section. v fb (pin 6): error amplifier inverting input. the noninverting input of the error amplifier is connected to an internal 1.231v reference. desired converter output volt- age (v out ) is programmed by connecting a resistive divider from the converter output to the v fb pin. values for the resistor connected from v out to v fb (r2) and the resistor connected from v fb to ground (r1) can be calcu- lated via the following relationship: rr v out 21 1 231 1 = ? ? ? ? ? ? . the v fb pin input bias current is 25na, so use of extremely high value feedback resistors could cause a converter output that is slightly higher than expected. bias current error at the output can be estimated as: ? v out(bias) = 25na ?r2 v c (pin 7): error amplifier output. the voltage on the v c pin corresponds to the maximum (peak) switch current per oscillator cycle. the error amplifier is typically config- ured as an integrator by connecting an rc network from this pin to ground. this network creates the dominant pole for the converter voltage regulation feedback loop. spe- cific integrator characteristics can be configured to opti- mize transient response. connecting a 100pf or greater high frequency bypass capacitor from this pin to ground is also recommended. when burst mode operation is enabled (see pin 5 description), an internal low impedance uu u pi fu ctio s clamp on the v c pin is set at 100mv below the burst threshold, which limits the negative excursion of the pin voltage. therefore, this pin cannot be pulled low with a low-impedance source. if the v c pin must be externally manipulated, do so through a 1k ? series resistance. sense (pin 8): negative input for current sense ampli- fier. sensed inductor current limit set at 150mv across sense inputs. sense + (pin 9): positive input for current sense ampli- fier. sensed inductor current limit set at 150mv across sense inputs. pgnd (pin 10): high current ground reference for syn- chronous switch. current path from pin to negative termi- nal of v cc decoupling capacitor must not corrupt sgnd. bg (pin 11): synchronous switch gate drive output. v cc (pin 12): internal regulator output. most ic func- tions are powered from this pin. driving this pin from an external source reduces v in pin current to 20 a. this pin is decoupled with a low esr 1 f capacitor to pgnd. in shutdown mode, this pin sinks 20 a until the pin voltage is discharged to 0v. see typical performance characteristics. nc (pin 13): no connection. sw (pin 14): reference for v boost supply and high current return for bootstrapped switch. tg (pin 15): bootstrapped switch gate drive output. boost (pin 16): bootstrapped supply ?maximum oper- ating voltage (ground referred) to 75v. this pin is decoupled with a low esr 1 f capacitor to pin sw. the voltage on the decoupling capacitor is refreshed through a rectifier from either v cc or an external source. exposed package backside (sgnd) (pin 17): low noise ground reference. sgnd connection is made through the exposed lead frame on back of tssop package which must be soldered to the pcb ground.
lt3800 7 3800fb fu ctio al diagra u u w + + + + + v in uvlo (<4v) bst uvlo 8v reg feedback reference + 1.231v 3.8v reg internal supply rail 1 16 15 14 12 10 9 17 3 5 7 4 6 v in v cc uvlo (<6v) shdn drive control drive control nol switch logic drive control burst_en v c c ss sense v fb + 1.185v 1v 0.5v error amp 2 a burst mode operation 8 soft-start disable/burst enable r s q oscillator slope comp generator boost tg sw v cc 11 bg pgnd sense + gnd 3800 fd boosted switch driver current sense comparator g m ? r s q + 160mv synchronous switch driver reverse current inhibit 10mv +
lt3800 8 3800fb overview the lt3800 is a high input voltage range step-down synchronous dc/dc converter controller ic that uses a 200khz constant frequency, current mode architecture with external n-channel mosfet switches. the lt3800 has provisions for high efficiency, low load operation for battery-powered applications. burst mode operation reduces total average input quiescent currents to 100 a during no load conditions. a low current shutdown mode can also be activated, reducing quiescent current to <10 a. burst mode operation can be disabled if desired. the lt3800 also employs a reverse-current inhibit fea- ture, allowing increased efficiencies during light loads through nonsynchronous operation. this feature disables the synchronous switch if inductor current approaches zero. if full time synchronous operation is desired, this feature can be disabled. much of the lt3800? internal circuitry is biased from an internal linear regulator. the output of this regulator is the v cc pin, allowing bypassing of the internal regulator. the associated internal circuitry can be powered from the output of the converter, increasing overall converter effi- ciency. using externally derived power also eliminates the ic? power dissipation associated with the internal v in to v cc regulator. theory of operation (see block diagram) the lt3800 senses converter output voltage via the v fb pin. the difference between the voltage on this pin and an internal 1.231v reference is amplified to generate an error voltage on the v c pin which is, in turn, used as a threshold for the current sense comparator. during normal operation, the lt3800 internal oscillator runs at 200khz. at the beginning of each oscillator cycle, the switch drive is enabled. the switch drive stays enabled until the sensed switch current exceeds the v c derived threshold for the current sense comparator and, in turn, disables the switch driver. if the current comparator applicatio s i for atio wu u u threshold is not obtained for the entire oscillator cycle, the switch driver is disabled at the end of the cycle for 450ns. this minimum off-time mode of operation assures regen- eration of the boost bootstrapped supply. power requirements the lt3800 is biased using a local linear regulator to generate internal operational voltages from the v in pin. virtually all of the circuitry in the lt3800 is biased via an internal linear regulator output (v cc ). this pin is decoupled with a low esr 1 f capacitor to pgnd. the v cc regulator generates an 8v output provided there is ample voltage on the v in pin. the v cc regulator has approximately 1v of dropout, and will follow the v in pin with voltages below the dropout threshold. the lt3800 has a start-up requirement of v in > 7.5v. this assures that the onboard regulator has ample headroom to bring the v cc pin above its uvlo threshold. the v cc regulator can only source current, so forcing the v cc pin above its 8v regulated voltage allows use of externally derived power for the ic, minimizing power dissipation in the ic. using the onboard regulator for start-up, then deriving power for v cc from the converter output maxi- mizes conversion efficiencies and is common practice. if v cc is maintained above 6.5v using an external source, the lt3800 can continue to operate with v in as low as 4v. the lt3800 operates with 3ma quiescent current from the v cc supply. this current is a fraction of the actual v cc quiescent currents during normal operation. additional current is produced from the mosfet switching currents for both the boosted and synchronous switches and are typically derived from the v cc supply. because the lt3800 uses a linear regulator to generate v cc , power dissipation can become a concern with high v in voltages. gate drive currents are typically in the range of 5ma to 15ma per mosfet, so gate drive currents can create substantial power dissipation. it is advisable to derive v cc and v boost power from an external source whenever possible.
lt3800 9 3800fb the onboard v cc regulator will provide gate drive power for start-up under all conditions with total mosfet gate charge loads up to 180nc. the regulator can operate the lt3800 continuously, provided the v in voltage and/or mosfet gate charge currents do not create excessive power dissipation in the ic. safe operating conditions for continuous regu- lator use are shown in figure 1. in applications where these conditions are exceeded, v cc must be derived from an external source after start-up. applicatio s i for atio wu uu charge pump doubler total fet gate charge (nc) 0 10 v in (v) 20 30 40 50 60 70 50 100 150 200 3800 f01 safe operating conditions figure 1. v cc regulator continuous operating conditions v out 1 f b0520 b0520 1 f si1555dl lt3800 v cc bg v out 1 f b0520 b0520 1 f 1 f si1555dl si1555dl lt3800 v cc bg b0520 3800 ai01 tg v out 3800 ai04 v cc sw bg n lt3800 inductor auxiliary winding charge pump tripler in lt3800 converter applications with output voltages in the 9v to 20v range, back-feeding v cc and v boost from the converter output is trivial, accomplished by connect- ing diodes from the output to these supply pins. deriving these supplies from output voltages greater than 20v will require additional regulation to reduce the feedback volt- age. outputs lower than 9v will require step-up techniques to increase the feedback voltage to something greater than the 8v v cc regulated output. low power boost switchers are sometimes used to provide the step-up function, but a simple charge-pump can perform this function in many instances.
lt3800 10 3800fb burst mode the lt3800 employs low current burst mode functionality to maximize efficiency during no load and low load condi- tions. burst mode operation is enabled by shorting the burst_en pin to sgnd. burst mode operation can be disabled by shorting burst_en to either v fb or v cc . when the required switch current, sensed via the v c pin voltage, is below 15% of maximum, the burst mode operation is employed and that level of sense current is latched onto the ic control path. if the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. this overdrive condition is sensed internally and forces the voltage on the v c pin to continue to drop. when the voltage on v c drops 150mv below the 15% load level, switching is disabled and the lt3800 shuts down most of its internal circuitry, reducing total quiescent current to 100 a. when the converter output begins to fall, the v c pin voltage begins to climb. when the voltage on the v c pin climbs back to the 15% load level, the ic returns to normal operation and switching resumes. an internal clamp on the v c pin is set at 100mv below the switch disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during burst mode operation. during burst mode operation, v in pin current is 20 a and v cc current is reduced to 80 a. if no external drive is provided for v cc , all v cc bias currents originate from the v in pin, giving a total v in current of 100 a. burst current can be reduced further when v cc is driven using an output derived source, as the v cc component of v in current is then reduced by the converter buck ratio. reverse-current inhibit the lt3800 contains a reverse-current inhibit feature to maximize efficiency during light load conditions. this mode of operation allows discontinuous operation, and is sometimes referred to as ?ulse-skipping?mode. refer to figure 2. this feature is enabled with burst mode operation, and can also be enabled while burst mode operation is disabled by shorting the burst_en pin to v fb . when reverse-current inhibit is enabled, the lt3800 sense amplifier detects inductor currents approaching zero and disables the synchronous switch for the remainder of the switch cycle. if the inductor current is allowed to go negative before the synchronous switch is disabled, the switch node could inductively kick positive with a high dv/dt. the lt3800 prevents this by incorporating a 10mv positive offset at the sense inputs. applicatio s i for atio wu uu pulse skip mode i l i l forced continuous decreasing load current 3800 f02 figure 2. inductor current vs mode
lt3800 11 3800fb with the reverse-current inhibit feature enabled, an lt3800 converter will operate much like a nonsynchronous converter during light loads. reverse-current inhibit re- duces resistive losses associated with inductor ripple currents, which improves operating efficiencies during light-load conditions. an lt3800 dc/dc converter that is operating in reverse- inhibit mode has a minimum load requirement of 1ma (burst_en = v fb ). since most applications use output- generated power for the lt3800, this requirement is met by the bias currents of the ic, however, for applications that do not derive power from the output, this require- ment is easily accomplished by using a 1.2k resistor connected from v fb to ground as one of the converter output voltage programming resistors (r1). there are no minimum load restrictions when in burst mode operation (burst_en < 0.5v) or continuous conduction mode (burst_en > 2.5v). soft-start the lt3800 incorporates a programmable soft-start func- tion to control start-up surge currents, limit output over- shoot and for use in supply sequencing. the soft-start function directly monitors and controls output voltage slew rate during converter start-up. as the output voltage of the converter rises, the soft-start circuit monitors v/ t current through a coupling capaci- tor and adjusts the voltage on the v c pin to maintain an average value of 2 a. the soft-start function forces the programmed slew rate while the converter output rises to 95% regulation, which corresponds to 1.185v on the v fb pin. once 95% regulation is achieved, the soft-start circuit is disabled. the soft-start circuit will re-enable when the v fb pin drops below 70% regulation, which corresponds to 300mv of control hysteresis on the v fb pin, which allows for a controlled recovery from a ?rown-out?condition. the desired soft-start rise time (t ss ) is programmed via a programming capacitor c ss1 , using a value that corresponds to 2 a average current during the soft-start interval. this capacitor value follows the relation: c e ss1 6 2 = ? v ss out r ss is typically set to 200k for most applications. applicatio s i for atio wu uu c ss v out c ss1 r ss a 3800 ai06 lt3800 considerations for low voltage output applications the lt3800 c ss pin biases to 220mv during the soft-start cycle, and this voltage is increased at network node ??by the 2 a signal current through r ss , so the output has to reach this value before the soft-start function is engaged. the value of this output soft-start start-up voltage offset (v out(ss) ) follows the relation: v out(ss) = 220mv + r ss ?2e ? which is typically 0.64v for r ss = 200k. in some low voltage output applications, it may be desir- able to reduce the value of this soft-start start-up voltage offset. this is possible by reducing the value of r ss . with reduced values of r ss , the signal component caused by voltage ripple on the output must be minimized for proper soft-start operation. peak-to-peak output voltage ripple ( ? v out ) will be im- posed on node ??through the capacitor c ss1 . the value of r ss can be set using the following equation: r v ss out = ? 1.3e ? it is important to use low esr output capacitors for lt3800 voltage converter designs to minimize this ripple voltage component. a design with an excessive ripple component can be evidenced by observing the v c pin during the start cycle.
lt3800 12 3800fb the soft-start cycle should be evaluated to verify that the reduced r ss value allows operation without excessive modulation of the v c pin before finalizing the design. if the v c pin has an excessive ripple component during the soft-start cycle, converter output ripple should be reduced or r ss increased. reduction in converter output ripple is typically accomplished by increasing output capacitance and/or reducing output capacitor esr. external current limit foldback circuit an additional start-up voltage offset can occur during the period before the lt3800 soft-start circuit becomes ac- tive. before the soft-start circuit throttles back the v c pin in response to the rising output voltage, current as high as the peak programmed current limit (i max ) can flow in the inductor. switching will stop once the soft-start circuit takes hold and reduces the voltage on the v c pin, but the output voltage will continue to increase as the stored energy in the inductor is transferred to the output capaci- tor. with i max flowing in the inductor, the resulting lead- ing-edge rise on v out due to energy stored in the inductor follows the relationship: ? = ? ? ? ? ? ? vi l c out max out / 12 applicatio s i for atio wu uu soft-start characteristic showing excessive ripple component desirable soft-start characteristic inductor current typically doesn? reach i max in the few cycles that occur before soft-start becomes active, but can with high input voltages or small inductors, so the above relation is useful as a worst-case scenario. this energy transfer increase in output voltage is typically small, but for some low voltage applications with relatively small output capacitors, it can become significant. the voltage rise can be reduced by increasing output capaci- tance, which puts additional limitations on c out for these low voltage supplies. another approach is to add an external current limit foldback circuit which reduces the value of i max during start-up. an external current limit foldback circuit can be easily incorporated into an lt3800 dc/dc converter application by placing a 1n4148 diode and a 47k resistor from the converter output (v out ) to the lt3800? v c pin. this limits the peak current to 0.25 ?i max when v out = 0v. a current limit foldback circuit also has the added advantage of providing a reduced output current in the dc/dc converter during short-circuit fault conditions, so a foldback circuit may be useful even if the soft-start function is disabled. if the soft-start circuit is disabled by shorting the c ss pin to ground, the external current limit fold-back circuit must be modified by adding an additional diode and resistor. the 2-diode, 2-resistor network shown also provides 0.25 ?i max when v out = 0v. v out v out(ss) v(v c ) 250 s/div 3800 ai07 v out v out(ss) v(v c ) 250 s/div 3800 ai08
lt3800 13 3800fb adaptive nonoverlap (nol) output stage the fet driver output stages implement adaptive nonoverlap control. this feature maintains a constant dead time, preventing shoot-through switch currents, independent of the type, size or operating conditions of the external switch elements. each of the two switch drivers contains a nol control circuit, which monitors the output gate drive signal of the other switch driver. the nol control circuits interrupt the ?urn on?command to their associated switch driver until the other switch gate is fully discharged. antislope compensation most current mode switching controllers use slope com- pensation to prevent current mode instability. the lt3800 is no exception. a slope-compensation circuit imposes an artificial ramp on the sensed current to increase the rising slope as duty cycle increases. unfortunately, this addi- tional ramp corrupts the sensed current value, reducing the achievable current limit value by the same amount as the added ramp represents. as such, current limit is typically reduced as duty cycles increase. the lt3800 contains circuitry to eliminate the current limit reduction typically associated with slope compensation. as the slope-compensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold reference. the end result is that current limit is not compromised, so a lt3800 converter can provide full power regardless of required duty cycle. applicatio s i for atio wu uu shutdown the lt3800 shdn pin uses a bandgap generated refer- ence threshold of 1.35v. this precision threshold allows use of the shdn pin for both logic-level controlled appli- cations and analog monitoring applications such as power supply sequencing. the lt3800 operational status is primarily controlled by a uvlo circuit on the v cc regulator pin. when the ic is enabled via the shdn pin, only the v cc regulator is en- abled. switching remains disabled until the uvlo thresh- old is achieved at the v cc pin, when the remainder of the ic is enabled and switching commences. because an lt3800 controlled converter is a power trans- fer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourc- ing capabilities of that supply, causing the system to lock up in an undervoltage state. input supply start-up protec- tion can be achieved by enabling the shdn pin using a resistive divider from the v in supply to ground. setting the divider output to 1.35v when that supply is at an adequate voltage prevents an lt3800 converter from drawing large currents until the input supply is able to provide the required power. 120mv of input hysteresis on the shdn pin allows for almost 10% of input supply droop before disabling the converter. v c v out 1n4148 3800 ai09 47k v c v out 1n4148 1n4148 3800 ai10 39k 27k current limit foldback circuit for applications that use soft-start alternative current limit foldback circuit for applications that have soft-start disabled
lt3800 14 3800fb the uvlo voltage, v in(uvlo) , is set using the following relation: rr vv v ab in uvlo = ? . () 135 135 if additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the lt3800 regulator output. the shutdown function can be disabled by connecting the shdn pin to v in through a large value pull-up resistor. this pin contains a low impedance clamp at 6v, so the shdn pin will sink current from the pull-up resistor (r pu ): i vv r shdn in pu = ? because this arrangement will pull the shdn pin to the 6v clamp voltage, it will violate the 5v absolute maximum voltage rating of the pin. this is permitted, however, as long as the absolute maximum input current rating of 1ma is not exceeded. input shdn pin currents of <100 a are recommended; a 1m ? or greater pull-up resistor is typi- cally used for this configuration. inductor selection the primary criterion for inductor value selection in lt3800 applications is ripple current created in that inductor. basic design considerations for ripple current are output voltage ripple, and the ability of the internal slope compen- sation waveform to prevent current mode instability. once the value is determined, an inductor must also have a saturation current equal to or exceeding the maximum peak current in the inductor. ripple current ( ? i l ) in an inductor for a given value (l) can be approximated using the relation: ? = ? ? ? ? ? ? i v v v fl l out in out o 1 the typical range of values for ? i is 20% to 40% of i out(max) , where i out(max) is the maximum converter output load current. ripple currents in this range typically yield a good design compromise between inductor perfor- mance versus inductor size and cost, and values in this range are generally a good starting point. a starting point inductor value can thus be determined using the relation: lv v v fi out out in o out max = ? ? ? ? ? ? ? () 1 03 use of smaller inductors increase output ripple currents, requiring more capacitance on the converter output. also, with converter operation with duty cycles greater than 50%, the slope compensation criterion, described later, must be met. designing for smaller ripple currents re- quires larger inductor values, which can increase con- verter cost and/or footprint. applicatio s i for atio wu uu programming lt3800 v in uvlo 3800 ai02 lt3800 v in r b r a 3 17 shdn sgnd
lt3800 15 3800fb some magnetics vendors specify a volt-second product in their data sheet. if they do not, consult the vendor to make sure the specification is not being exceeded by your design. the required volt-second product is calculated as follows: volt f v v o out in - second v out ? ? ? ? ? ? 1 magnetics vendors specify either the saturation current, the rms current, or both. when selecting an inductor based on inductor saturation current, the peak current through the inductor, i out(max) + ( ? i/2), is used. when selecting an inductor based on rms current the maximum load current, i out(max) , is used. the requirement for avoiding current mode instability is keeping the rising slope of sensed inductor ripple current (s1) greater than the falling slope (s2). during continuous- current switcher operation, the rising slope of the current waveform in the switched inductor is less than the falling slope when operating at duty cycles (dc) greater than 50%. to avoid the instability condition during this operation, a false signal is added to the sensed current, increasing the perceived rising slope. to prevent current mode instabil- ity, the slope of this false signal (sx) must be sufficient such that the sensed rising slope exceeds the falling slope, or s1 + sx s2. this leads to the following relations: sx s2 (2dc ?1)/dc where: s2 ~ v out /l solving for l yields a relation for the minimum inductance that will satisfy slope compensation requirements: lv dc dc sx min out = 21 the lt3800 maximizes available dynamic range using a slope compensation generator that continuously increases the additional signal slope as duty cycle increases. the slope compensation waveform is calibrated at an 80% duty cycle, to generate an equivalent slope of at least 1e 5 ?i limit a/sec, where i limit is the programmed con- verter current limit. current limit is programmed by using a sense resistor (r s ) such that i limit = 150mv/r s , so the equation for the minimum inductance to meet the current mode instability criterion can be reduced to: l min = (5e ? )(v out )(r s ) for example, with v out = 5v and r s = 20m ? : l min = (5e ? )(5)(0.02) = 5 h after calculating the minimum inductance value, the volt- second product, the saturation current and the rms current for your design, an off the shelf inductor can be selected from a magnetics vendor. a list of magnetics vendors can be found at http://www.linear.com/ezone/ vlinks or by contacting the linear technology applications department. output voltage programming output voltage is programmed through a resistor feed- back network to v fb (pin 6) on the lt3800. this pin is the inverting input of the error amplifier, which is internally referenced to 1.231v. the divider is ratioed to provide 1.231v at the v fb pin when the output is at its desired value. the output voltage is thus set following the relation: rr v out 21 1 231 1 = ? ? ? ? ? ? . when an external resistor divider is connected to the output as shown. applicatio s i for atio wu uu programming lt3800 output voltage 3800 ai03 lt3800 v out r2 r1 6 17 v fb sgnd
lt3800 16 3800fb power mosfet selection external n-channel mosfet switches are used with the lt3800. the positive gate-source drive voltage of the lt3800 for both switches is roughly equivalent to the v cc supply voltage, for use of standard threshold mosfets. selection criteria for the power mosfets include the ?n resistance (r ds(on) ), total gate charge (q g ), reverse transfer capacitance (c rss ), maximum drain-source voltage (v dss ) and maximum current. the power fets selected must have a maximum operating v dss exceeding the maximum v in . v gs voltage maximum must exceed the v cc supply voltage. total gate charge (q g ) is used to determine the fet gate drive currents required. q g increases with applied gate voltage, so the q g for the maximum applied gate voltage must be used. a graph of q g vs. v gs is typically provided in mosfet datasheets. in a configuration where the lt3800 linear regulator is providing v cc and v boost currents, the v cc 8v output voltage can be used to determine q g . required drive current for a given fet follows the simple relation: i gate = q g(8v) ?f o q g(8v) is the total fet gate charge for v gs = 8v, and f 0 = operating frequency. if these currents are externally de- rived by backdriving v cc , use the backfeed voltage to determine q g . be aware, however, that even in a backfeed configuration, the drive currents for both boosted and synchronous fets are still typically supplied by the lt3800 internal v cc regulator during start-up. the lt3800 can start using fets with a combined q g(8v) up to 180nc. once voltage requirements have been determined, r ds(on) can be selected based on allowable power dissipation and required output current. in an lt3800 buck converter, the average inductor current is equal to the dc load current. the average currents through the main (bootstrapped) and synchronous (ground-referred) switches are: i main = (i load )(dc) i sync = (i load )(1 ?dc) the r ds(on) required for a given conduction loss can be calculated using the relation: p loss = i switch 2 ?r ds(on) in high voltage applications (v in > 20v), the main switch is required to slew very large voltages. mosfet transition losses are proportional to v in 2 and can become the dominant power loss term in the main switch. this transi- tion loss takes the form: p tr (k)(v in ) 2 (i switch )(c rss )(f o ) where k is a constant inversely related to the gate drive current, approximated by k = 2 in lt3800 applications, and i switch is the converter output current. the power loss terms for the switches are thus: p main = (dc)(i switch ) 2 (1 + d)(r ds(on) ) + 2(v in ) 2 (i switch )(c rss )(f o ) p sync = (1 ?dc)(i switch ) 2 (1 + d)(r ds(on) ) the (1 + d) term in the above relations is the temperature dependency of r ds(on) , typically given in the form of a normalized r ds(on) vs temperature curve in a mosfet data sheet. the c rss term is typically smaller for higher voltage fets, and it is often advantageous to use a fet with a higher v ds rating to minimize transition losses at the expense of additional r ds(on) losses. in some applications, parasitic fet capacitances couple the negative going switch node transient onto the bottom gate drive pin of the lt3800, causing a negative voltage in excess of the absolute maximum rating to be imposed on that pin. connection of a catch schottky diode from this pin to ground will eliminate this effect. a 1a current rating is typically sufficient for the diode. applicatio s i for atio wu uu
lt3800 17 3800fb input capacitor selection the large currents typical of lt3800 applications require special consideration for the converter input and output supply decoupling capacitors. under normal steady state buck operation, the source current of the main switch mosfet is a square wave of duty cycle v out /v in . most of this current is provided by the input bypass capacitor. to prevent large input voltage transients and avoid bypass capacitor heating, a low esr input capacitor sized for the maximum rms current must be used. this maximum capacitor rms current follows the relation: i ivvv v rms max out in out in = () () 1 2 which peaks at a 50% duty cycle, when i rms = i max /2. the bulk capacitance is calculated based on an acceptable maximum input ripple voltage, ? v in , which follows the relation: ci v v vf in bulk out max out in in o () () = ? ? v is typically on the order of 100mv to 200mv. alumi- num electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. the capacitor voltage rating must be rated greater than v in(max) . the combination of aluminum electrolytic ca- pacitors and ceramic capacitors is a common approach to meeting supply input capacitor requirements. multiple capacitors are also commonly paralleled to meet size or height requirements in a design. capacitor ripple current ratings are often based on only 2000 hours (three months) lifetime; it is advisable to derate either the esr or temperature rating of the capaci- tor for increased mtbf of the regulator. output capacitor selection the output capacitor in a buck converter generally has much less ripple current than the input capacitor. peak-to- peak ripple current is equal to that in the inductor ( ? i l ), typically a fraction of the load current. c out is selected to reduce output voltage ripple to a desirable value given an expected output ripple current. output ripple ( ? v out ) is approximated by: ? v out ? i l (esr + [(8)(f o ) ?c out ] ? ) where f o = operating frequency. ? v out increases with input voltage, so the maximum operating input voltage should be used for worst-case calculations. multiple capacitors are often paralleled to meet esr requirements. typically, once the esr require- ment is satisfied, the capacitance is adequate for filtering and has the required rms current rating. an additional ceramic capacitor in parallel is commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. increasing inductance is an option to reduce esr require- ments. for extremely low ? v out, an additional lc filter stage can be added to the output of the supply. applica- tion note 44 has information on sizing an additional output lc filter. layout considerations the lt3800 is typically used in dc/dc converter designs that involve substantial switching transients. the switch drivers on the ic are designed to drive large capacitances and, as such, generate significant transient currents them- selves. careful consideration must be made regarding supply bypass capacitor locations to avoid corrupting the ground reference used by ic. typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from sgnd, to which sensitive circuits such as the error amp reference and the current sense circuits are referred. applicatio s i for atio wu uu
lt3800 18 3800fb effective grounding can be achieved by considering switch current in the ground plane, and the return current paths of each respective bypass capacitor. the v in bypass return, v cc bypass return, and the source of the synchro- nous fet carry pgnd currents. sgnd originates at the negative terminal of the v out bypass capacitor, and is the small signal reference for the lt3800. don? be tempted to run small traces to separate ground paths. a good ground plane is important as always, but pgnd referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the sgnd reference. during the dead-time between switch conduction, the body diode of the synchronous fet conducts inductor current. commutating this diode requires a significant charge contribution from the main switch. at the instant the body diode commutates, a current discontinuity is created and parasitic inductance causes the switch node to fly up in response to this discontinuity. high currents and excessive parasitic inductance can generate extremely fast dv/dt rise times. this phenomenon can cause avalanche breakdown in the synchronous fet body di- ode, significant inductive overshoot on the switch node, and shoot-through currents via parasitic turn-on of the synchronous fet. layout practices and component ori- entations that minimize parasitic inductance on this node is critical for reducing these effects. ringing waveforms in a converter circuit can lead to device failure, excessive emi, or instability. in many cases, you can damp a ringing waveform with a series rc network across the offending device. in lt3800 applica- tions, any ringing will typically occur on the switch node, which can usually be reduced by placing a snubber across the synchronous fet. use of a snubber network, however, should be considered a last resort. effective layout prac- tices typically reduce ringing and overshoot, and will eliminate the need for such solutions. effective grounding techniques are critical for successful dc/dc converter layouts. orient power path components such that current paths in the ground plane do not cross through signal ground areas. signal ground refers to the exposed pad on the backside of the lt3800 ic. sgnd is referenced to the (? terminal of the v out decoupling capacitor and is used as the converter voltage feedback reference. power ground currents are controlled on the lt3800 via the pgnd pin, and this ground references the high current synchronous switch drive components, as well as the local v cc supply. it is important to keep pgnd and sgnd voltages consistent with each other, so sepa- rating these grounds with thin traces is not recommended. when the synchronous fet is turned on, gate drive surge currents return to the lt3800 pgnd pin from the fet source. the boost supply refresh surge currents also return through this same path. the synchronous fet must be oriented such that these pgnd return currents do not corrupt the sgnd reference. problems caused by the pgnd return path are generally recognized during heavy load conditions, and are typically evidenced as multiple switch pulses occurring during a single 5 s switch cycle. this behavior indicates that sgnd is being corrupted and grounding should be improved. sgnd corruption can often be eliminated, however, by adding a small capacitor (100pf-200pf) across the synchronous switch fet from drain to source. the high di/dt loop formed by the switch mosfets and the input capacitor (c in ) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. surface mount components are pre- ferred to reduce parasitic inductances from component leads. connect the drain of the main switch mosfet directly to the (+) plate of c in , and connect the source of the synchronous switch mosfet directly to the (? termi- nal of c in . this capacitor provides the ac current to the switch mosfets. switch path currents can be controlled by orienting switch fets, the switched inductor, and input and output decoupling capacitors in close proximity to each other. locate the v cc and boost decoupling capacitors in close proximity to the ic. these capacitors carry the mosfet applicatio s i for atio wu uu
lt3800 19 3800fb boost v cc sw pgnd sgnd lt3800 sgnd referred components + + bg tg v out 3800 ai05 v in i sense sw orientation of components isolates power path and pgnd currents, preventing corruption of sgnd reference drivers?high peak currents. locate the small-signal compo- nents away from high frequency switching nodes (boost, sw, tg, v cc and bg). small-signal nodes are oriented on the left side of the lt3800, while high current switching nodes are oriented on the right side of the ic to simplify layout. this also helps prevent corruption of the sgnd reference. connect the v fb pin directly to the feedback resistors in- dependent of any other nodes, such as the sense pin. the feedback resistors should be connected between the (+) and (? terminals of the output capacitor (c out ). locate the feedback resistors in close proximity to the lt3800 to minimize the length of the high impedance v fb node. the sense and sense + traces should be routed to- gether and kept as short as possible. the lt3800 packaging has been designed to efficiently remove heat from the ic via the exposed pad on the backside of the package. the exposed pad is soldered to a copper footprint on the pcb. this footprint should be made as large as possible to reduce the thermal resistance of the ic case to ambient air. applicatio s i for atio wu uu
lt3800 20 3800fb typical applicatio s u 6.5v-55v to 5v 10a dc/dc converter with charge pump doubler v cc refresh and current limit foldback v in nc shdn c ss burst_en v fb v c sense boost tg sw nc v cc bg pgnd sense + lt3800 sgnd c7 1.5nf r3 62k r5 47k d2 1n4148 r4 75k c9 470pf c10 100pf r2 309k 1% r1 100k 1% r a 1m r s 0.01 ? d1 bas19 c1 1 f 16v x7r c3 1 f 16v x7r c2 1 f 100v x7r 3 c8 56 f 63v 2 + c6 10 f 6.3v x7r c5 220 f 2 + m1 si7850dp 2 m2 si7370dp 2 m3 1/2 si1555dl m4 1/2 si1555dl ds3 b160 2 ds1 mbro520l c4 1 f ds2 mbro520l l1 5.6 h v in 6.5v to 55v v out 5v at 10a 3800 ta02a c5: sanyo poscap 6tp220m l1: ihlp-5050fd-01 i out (a) 0 70 efficiency (%) power loss (w) 75 80 85 90 95 100 0 2 4 6 8 10 12 2468 3800 ta02b 10 v in = 13.8v v in = 55v v in = 24v v in = 48v power loss v in = 48v power loss v in = 13.8v efficiency and power loss
lt3800 21 3800fb typical applicatio s u 9v-38v to 3.3v 10a dc/dc converter with input uvlo and burst mode operation no load i(v in ) = 100 a efficiency and power loss v in nc shdn c ss burst_en v fb v c sense boost tg sw nc v cc bg pgnd sense + lt3800 sgnd c1 1nf c3 100pf c2 330pf c10 100pf r2 169k 1% r1 100k 1% r4 39k r3 82k r a 1m r b 187k r s 0.01 ? d1 mbr520 c5 1 f 16v x7r c4 1 f 16v x7r c9 4.7 f 50v x7r 3 c8 100 f 50v 2 + c7 10 f 6.3v x7r c6 470 f 2 + m1 si7884dp m2 si7884dp ds1 ss14 2 l1 3.3 h v in 9v to 38v v out 3.3v at 10a 3800 ta03a c6: sanyo poscap 4tpd470m l1: ihlp-5050fd-01 i load (a) 78 84 82 80 92 90 88 86 0 3 2 1 7 6 5 4 3800 ta03b efficiency (%) power loss (w) 0.1 10 1 v in = 13.8v
lt3800 22 3800fb typical applicatio s u v in nc shdn c ss burst_en v fb v c sense boost tg sw nc v cc bg pgnd sense + lt3800 sgnd c1 3.9nf c9 1nf c3 100pf c2 1nf c6 47pf r2 154k 1% r1 49.9k 1% r5 47k d2 1n4148 r4 51k r3 27k r a 1m r b 187k r s 0.02 ? d1 bas19 c5 1 f 10v x7r c4 1 f 10v x7r c8 22 f 3 c7 100 f 2 m1 si7884dp m2 si7884dp ds1 ss14 l1 10 h v in 9v to 38v v out 5v at 6a 3800 ta05a c7: tdk c4532x5r0j107mt c8: tdk c5750x7r1e226mt l1: ihlp-5050fd-01 9v-38v to 5v 6a dc/dc converter with all ceramic capacitors, input uvlo, burst mode operation and current limit foldback efficiency and power loss i load (a) 70 efficiency (%) power loss (w) 80 85 95 100 0.001 0.1 1 10 3800 ta05b 60 0.01 90 75 65 0.80 1.60 2.00 2.80 3.20 0 2.40 1.20 0.40 v in = 13.8v
lt3800 23 3800fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc package descriptio u fe16 (bc) tssop 0204 0.09 ?0.20 (.0035 ?.0079) 0 ?8 0.25 ref 0.50 ?0.75 (.020 ?.030) 4.30 ?4.50* (.169 ?.177) 134 5 6 7 8 10 9 4.90 ?5.10* (.193 ?.201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ?0.15 (.002 ?.006) 0.65 (.0256) bsc 2.94 (.116) 0.195 ?0.30 (.0077 ?.0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
lt3800 24 3800fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 1007 rev b ? printed in usa 24v-48v to ?2v 75w inverting dc/dc converter with v in uvlo related parts part number description comments ltc1735 synchronous step-down controller 4v v in 36v, 0.8v v out 6v, i out 20a ltc1778 no r sense tm synchronous step-down controller current mode without using sense resistor, 4v v in 36v lt 1934 micropower step-down switching regulator 3.2v v in 34v, 300ma switch, thinsot tm package lt1952 synchronous single switch forward converter 25w to 500w isolated power supplies, small size, high efficiency lt1976 60v switching regulator 3.2v v in 60v, 1.5a switch, 16-lead tssop lt3010 3v to 80v ldo 50ma output current, 1.275v v out 60v lt3430/lt3431 3a, 60v switching regulators 5.5v v in 60v, 200khz, 16-lead tssop ltc3703 100v synchronous step-down controller large 1 ? gate drivers, no r sense ltc3703-5 60v synchronous step-down controller large 1 ? gate drivers, no r sense ltc3727-1 high v out 2-phase dual step-down controller 0.8v v out 14v, pll: 250khz to 550khz ltc3728l 2-phase, dual synchronous step-down controller 550khz, pll: 250khz to 550khz, 4v v in 36v no r sense and thinsot are trademarks of linear technology corporation. v in nc shdn c ss burst_en v fb v c sense boost tg sw nc v cc bg pgnd sense + lt3800 sgnd c1 1nf r1 200k c3 470pf r8 1m r3 1m r7 1m r6 130k r4 39k r5 20k 1% r2 174k 1% c2 1 f 16v x7r c4 100pf c8 4.7 f 16v x7r c5 270 f 16v sprague sp c7 150pf 100v d2 1n4148 d1 bas19 c9 56 f 63v 2 c10 1 f 100v x7r 4 c6 1 f 16v x7r m1 fdd3570 m2 fdd3570 l1: coev mgpwl-00099 v in 24v to 48v v out ?2v 75w r s 0.01 ? l1 15 h ds1 b180 2n3906 3800 ta04a + + i load (a) 0.1 40 efficiency (%) power loss (w) 50 60 70 80 100 110 3800 ta04b 90 0 2 4 6 8 12 10 v in = 24v v in = 48v v in = 36v loss v in = 36v efficiency and power loss typical applicatio u

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